Renesas Electronics /R7FA6T2BD /ADC_B /ADTRGDLR0

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Interpret as ADTRGDLR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRGDLY00TRGDLY1

Description

A/D Conversion Start Trigger Delay Register 0

Fields

TRGDLY0

Scan Group 0 Trigger Input Delay Configuration

TRGDLY1

Scan Group 1 Trigger Input Delay Configuration

Links

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